The present invention is related to subject matter disclosed in the following co-pending patent applications:
1. United States patent application entitled, xe2x80x9cProcess for Treating ONO Dielectric Film of a Floating Gate Memory Cellxe2x80x9d, U.S. patent application Ser. No. 09/927,133 naming Robert B. Ogle, Jr. and Arvind Halliyal as inventors and filed on Aug. 10, 2001; and
2. United States patent application entitled, xe2x80x9cProcess for Treating ONO Dielectric Film of a Floating Gate Memory Cellxe2x80x9d, U.S. patent application Ser. No. 09/927,988 naming Robert B. Ogle, Jr. and Arvind Halliyal as inventors and filed on Aug. 10, 2001.
1. Field of Invention
The present invention relates to semiconductor processing. More specifically, it relates to processing an ONO dielectric film of a floating gate memory cell in a NO or N2O ambient environment.
2. Related Art
Non-volatile semiconductor memories, such as EEPROM (Electrically Erasable Programmable Read Only Memory) utilize stacked floating gate type field effect transistors. Conventionally, electrons are induced into a floating gate of a memory cell to be programmed by biasing a control gate at a certain voltage, and grounding the body region. The substrate is biased, while the control gate is grounded driving the electrons from the floating gate back into the substrate.
FIG. 1 is a cross sectional diagram of a floating gate memory cell 100. Memory cell 100 is a floating gate transistor having a control gate 102 coupled to a voltage line 122 for applying a voltage of Vg on control gate 102. Control gate 102 is separated from a floating gate 106 by an upper insulating layer 104. The floating gate 106 is separated from a substrate 110 by a lower insulating layer 108.
Substrate 110 includes an n+ source region 112 coupled to a voltage line 132 for applying a voltage of Vs on n+ source region 112, a p-doped body region 114 coupled to a voltage line 134 for applying a voltage on p-doped body region 114, and an n+ drain region 116 coupled to a voltage line 136 for applying a voltage of VD on n+ drain region 116.
Insulating layer 104 is a composite dielectric film surrounding floating gate 106 and insures that charge is retained in floating gate 106. One type of dielectric film used as an insulating layer consists of a stack of silicon dioxide-silicon nitride-silicon dioxide (xe2x80x9cONOxe2x80x9d) layers. The ONO stack 104 is used to isolate floating gate 106 and also couple high voltage from control gate 102 to floating gate 106. Electrical thickness of ONO stack 104 is in the range of 100 xc3x85 to 200 xc3x85.
FIG. 2 is a cross-sectional diagram of ONO layer 104. Currently, silicon dioxide (SiO2) layer 201 from 20 xc3x85 to 50 xc3x85 is formed by thermally oxidizing polysilicon floating gate 106, or by depositing a low pressure chemical vapor deposition (LPCVD) oxide (High Temperature Oxide (HTO)) or rapid thermal chemical vapor deposition (RTCVD) oxide. Silicon nitride (Si3N4) layer 202 from 50 xc3x85 to 100 xc3x85 is formed on SiO2 layer 201, by depositing LPCVD or RTCVD nitride.
A second layer of SiO2 203 from 20 xc3x85 to 60 xc3x85 is formed by steam oxidation of a part of Si3N4 layer 202. Conventionally, steam oxidation of the silicon nitride layer 202 is performed in a batch furnace at 900-1000 deg Celsius, preferably 950 deg Celsius.
Thermal oxidation of Si3N4 layer 202 is a slow process and the final thickness of the ONO layer is hard to scale for new generations of flash memory devices. A thermally deposited third layer of SiO2 (HTO) may be used but the resulting ONO stack is too leaky and hence unreliable.
Accordingly, a process is desired to form the second SiO2 layer that optimizes the characteristics of the ONO stack and maintains reliability of the ONO stack.
The present invention is a method for forming an ONO stack of a floating gate transistor with a first layer of SiO2 formed on the floating gate and a silicon nitride layer formed on the first SiO2 layer. Thereafter, a second layer of silicon dioxide is thermally deposited on the silicon nitride layer, and the ONO stack is annealed in either a batch furnace or a single wafer rapid thermal annealing tool.
The annealing process in the batch furnace is performed at a temperature range of 800 to 1050 deg Celsius from 5 to 30 minutes with a gas mixture of 5% to 100% of either nitrogen oxide (NO) or nitrous oxide (N2O) with argon, nitrogen and/or oxygen as carrier gases.
The annealing process in the single wafer rapid thermal annealing tool is performed at a temperature range of 700 to 1100 deg Celsius from 1 second to 120 seconds with a gas mixture of 1% to 100% NO or N2O with argon, nitrogen and/or oxygen as carrier gases.
The advantages of the present invention include reducing the processing time for forming the second SiO2 layer, reducing the thickness of the second SiO2 and minimizing change to the silicon nitride layer and hence improving overall reliability of the ONO stack.